V. The internal pullup for each pin is used to hold the pin high, and a high-to-low transition on the pin triggers. Each button is connected to a GPIO pin and an interrupt is used for each input to determine whether the user has pressed that button. Proc_interrupt_handler_sub.asm _proc_int_handle_interrupt_subroutine I have a device that has several buttons. _res_core_enable_irq_interrupt() /* cpsie i */ * Enable IRQ - Clear I flag in CPS register */ Io_gio_clear_sync_irq() /* gioREG->FLG = 1U */ After an interrupt is claimed, the relevant bit of interrupt pending ( IP) is cleared, regardless of the status of the intrsrci input value. Io_init() /* Initialize of IO Driver component */ The PRUSS interrupt controller (INTC) is an hardware interface between interrupts coming from different parts of the system (these are referred to as system events), and the PRUs interrupt inputs. Res_sys_intvecs.asm branch to res_start_bootstrap() Is it sufficient to clear pending interrupt (gioREG->FLG = 1U ) in the interrupt service routine? Clears the pending bit of an non-secure external interrupt when in secure state. We saw that the interrupt sometimes is executed, direct after the pending interrupt is cleared and the irq is enabled, although no HW pulse is generated on GPIO Bit0 pin. clear pending interrupt on GPIO pin Bit0 /* gioREG->FLG = 1U */ We have a extern HW timer that generates a pulse every 5 ms on the GPIO pin Bit0. Other Parts Discussed in Thread: TMS570LC4357
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